数字逻辑设计 VHDL 基础 英文版PDF|Epub|txt|kindle电子书版本网盘下载

数字逻辑设计 VHDL 基础 英文版PDF格式电子书版下载

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Chapter 1 DESIGN CONCEPTS 11

1．1 Digital Hardware2

1．1．1 Standard Chips4

1．1．2 Programmable Logic Devices4

1．1．3 Custom-Designed Chips5

1．2 The Design Process6

1．3 Design of Digital Hardware8

1．3．1 Basic Design Loop8

1．3．2 Design of a Digital Hardware Unit9

1．4 Logic Circuit Design in this Book12

1．5 Theory and Practice14

References15

Chapter 2 INTRODUCTION TO LOGIC CIRCUITS17

2．1 Variables and Functions18

2．2 Inversion21

2．3 Truth Tables22

2．4 Logic Gates and Networks23

2．4．1 Analysis of a Logic Network24

2．5 Boolean Algebra27

2．5．1 The Venn Diagram30

2．5．2 Notation and Terminology34

2．5．3 Precedence of Operations34

2．6 Synthesis Using AND，OR，and NOT Gates35

2．6．1 Sum-of-Products and Product-of-Sums Forms37

2．7 Design Examples41

2．7．1 Three Way Light Control42

2．7．2 Multiplexer Circuit43

2．8 Introduction to CAD Tools45

2．8．1 Design Entry46

2．8．2 Synthesis48

2．8．3 Functional Simulation49

2．8．4 Summary49

2．9 Introduction to VHDL51

2．9．2 Writing Simple VHDL Code52

4．2 Strategy for Minimization52

2．9．1 Representation of Digital Signals in VHDL52

2．9．3 How Not to Write VHDL Code54

2．10 Concluding Remarks55

Problems56

References60

Chapter 3 IMPLEMENTATION TECHNOLOGY61

3．1 Transistor Switches63

3．2 NMOS Logic Gates65

3．3 CMOS Logic Gates68

3．3．1 Speed of Logic Gate Circuits75

3．4 Negative Logic System76

3．5 Standard Chips77

3．5．1 7400-Series Standard Chips77

3．6 Programmable Logic Devices81

3．6．1 Programmable Logic Array(PLA)81

3．6．2 Programmable Array Logic(PAL)84

3．6．3 Programming of PLAs and PALs86

3．6．4 Complex Programmable Logic Devices (CPLDs)88

3．6．5 Field-Programmable Gate Arrays92

3．6．6 Using CAD Tools to Implement Circuits in CPLDs and FPGAs96

3．7 Custom Chips，Standard Cells，and Gate Arrays97

3．8 Practical Aspects100

3．8．1 MOSFET Fabrication and Behavior100

3．8．2 MOSFET On-Resistance104

3．8．3 Voltage Levels in Logic Gates105

3．8．4 Noise Margin107

3．8．5 Dynamic Operation of Logic Gates108

3．8．6 Power Dissipation in Logic Gates111

3．8．7 Passing Is and Os Through Transistor Switches112

3．8．8 Fan-in and Fan-out in Logic Gates114

3．9 Transmission Gates120

3．9．1 Exclusive-OR Gates121

3．9．2 Multiplexer Circuit122

3．10 Implementation Details for SPLDs，CPLDs，and FPGAs123

3．10．1 Implementation in FPGAs129

3．11 Concluding Remarks131

Problems132

References141

Chapter 4 OPTIMIZED IMPLEMENTATION OF LOGIC FUNCTIONS143

4．1 Karnaugh Map144

4．2．1 Terminology153

4．2．2 Minimization Procedure154

4．3 Minimization of Product-of-Sums Forms158

4．4 Incompletely Specified Functions160

4．5 Multiple-Output Circuits161

4．6 NAND and NOR Logic Networks165

4．7 Multilevel Synthesis167

4．7．1 Factoring168

4．7．2 Functional Decomposition171

4．7．3 Multilevel NAND and NOR Circuits177

4．8 Analysis of Multilevel Circuits180

4．9 Cubical Representation185

4．9．1 Cubes and Hypercubes185

4．10 Minimization Using Cubical Representation189

4．10．1 Generation of Prime Implicants189

4．10．2 Determination of Essential Prime Implicants192

4．10．3 Complete Procedure for Finding a Minimal Cover194

4．11 Practical Considerations196

4．12 CAD Tools197

4．12．1 Logic Synthesis and Optimization198

4．12．2 Physical Design199

4．12．3 Timing Simulation201

4．12．4 Summary of Design Flow202

4．12．5 Examples of Circuits Synthesized from VHDL Code204

4．13 Concluding Remarks210

Problems211

References214

Chapter 5 NUMBER REPRESENTATION AND ARITHMETIC CIRCUITS217

5．1 Positional Number Representation218

5．1．1 Unsigned Integers218

5．1．2 Conversion between Decimal and Binary Systems219

5．1．3 Octal and Hexadecimal Representations220

5．2 Addition of Unsigned Numbers222

5．2．1 Decomposed Full-Adder226

5．2．2 Ripple-Carry Adder227

5．2．3 Design Example228

5．3 Signed Numbers228

5．3．1 Negative Numbers228

5．3．2 Addition and Subtraction232

5．3．3 Adder and Subtractor Unit236

5．3．4 Radix-Complement Schemes237

5．3．5 Arithmetic Overflow241

5．3．6 Performance Issues242

5．4．1 Carrv-Lookahead Adder243

5．4 Fast Adders243

5．5 Design of Arithmetic Circuits Using CAD Tools250

5．5．1 Design of Arithmetic Circuits Using Schematic Capture250

5．5．2 Design of Arithmetic Circuits Using VHDL253

5．5．3 Representation of Numbers in VHDL Code256

5．5．4 Arithmetic Assignment Statements258

5．6 Multiplication262

5．6．1 Array Multiplier for Unsigned Numbers263

5．6．2 Multiplication of Signed Numbers264

5．7 Other Number Representations267

5．7．1 Fixed-Point Numbers267

5．7．2 Floating-Point Numbers267

5．7．3 Binary-Coded-Decimal Representation269

5．8 ASCII Character Code273

Problems276

References280

Chapter 6 COMBINATIONAL-CIRCUIT BUILDING BLOCKS281

6．1 Multiplexers282

6．1．1 Synthesis of Logic Functions Using Multiplexers287

6．1．2 Multiplexer Synthesis Using Shannon s Expansion288

6．2 Decoders295

6．2．1 Demultiplexers298

6．3 Encoders300

6．3．1 Binary Encoders300

6．3．2 Priority Encoders301

6．4 Code Converters302

6．5 Arithmetic Comparison Circuits304

6．6 VHDL for Combinational Circuits304

6．6．1 Assignment Statements305

6．6．2 Selected Signal Assignment305

6．6．3 Conditional Signal Assignment308

6．6．4 Generate Statements312

6．6．5 Concurrent and Sequential Assignment Statements315

6．6．6 Process Statement315

6．6．7 Case Statement321

6．7 Concluding Remarks324

Problems326

References330

Chapter 7 FLIP-FLOPS，REGISTERS，COUNTERS，AND A SIMPLE PROCESSOR331

7．1 Basic Latch333

7．2 Gated SR Latch335

7．2．1 Gated SR Latch with NAND Gates337

7．3 Gated D Latch338

7．3．1 Effects of Propagation Delays340

7．4 Master-Slave and Edge-Triggered D Flip-Flops341

7．4．1 Master-Slave D Flip-Flop341

7．4．2 Edge-Triggered D Flip-Flop342

7．4．3 D FLIP-Flops with Clear and Preset344

7．5 T Flip-Flop346

7．5．1 Configurable Flip-Flops349

7．6 JK Flip-Flop349

7．8 Registers350

7．7 Summary of Terminology350

7．8．1 Shift Register351

7．8．2 Parallel-Access Shift Register352

7．9 Counters353

7．9．1 Asynchronous Counters353

7．9．2 Synchronous Counters356

7．9．3 Counters with Parallel Load360

7．10 Reset Synchronization360

7．11 Other Types of Counters364

7．11．1 BCD Counter364

7．11．2 Ring Counter365

7．11．3 Johnson Counter366

7．12 Using Storage Elements with CAD Tools367

7．12．1 Including Storage Elements in Schematics367

7．11．4 Remarks on Counter Design367

7．12．2 Using Latches and Flip-Flops in VHDL Code370

7．12．3 Using VHDL Sequential Statements for Storage Elements370

7．13 Using Registers and Counters with CAD Tools375

7．13．1 Including Registers and Counters in Schematics375

7．13．2 Registers and Counters in VHDL Code378

7．13．3 Using VHDL Sequential Statements for Registers and Counters379

7．14 Design Examples387

7．14．1 Bus Structure387

7．14．2 Simple Processor400

7．14．3 Reaction Timer413

7．15 Concluding Remarks418

Problems418

References424

Chapter 8 SYNCHRONOUS SEQUENTIAL CIRCUITS427

8．1 Basic Design Steps429

8．1．1 State Diagram429

8．1．2 State Table431

8．1．3 State Assignment431

8．1．4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions433

8．1．5 Timing Diagram435

8．1．6 Summary of Design Steps436

8．2 State-Assignment Problem440

8．2．1 One-Hot Encoding442

8．3 Mealy State Model444

8．4 Design of Finite State Machines Using CAD Tools449

8．4．1 VHDL Code for Moore-Type FSMs449

8．4．2 Synthesis of VHDL Code451

8．4．3 Simulating and Testing the Circuit454

8．4．4 An Alternative Style of VHDL Code456

8．4．5 Summary of Design Steps When Using CAD Tools456

8．4．6 Specifying the State Assignment in VHDL Code458

8．4．7 Specification of Mealy FSMs Using VHDL459

8．5 Serial Adder Example463

8．5．1 Mealy-Type FSM for Serial Adder463

8．5．2 Moore-Type FSM for Serial Adder464

8．5．3 VHDL Code for the Serial Adder467

8．6 State Minimization470

8．6．1 Partitioning Minimization Procedure473

8．6．2 Incompletely Specified FSMs480

8．7．2 State Assignment482

8．7 Design of a Counter Using the Sequential Circuit Approach482

8．7．1 State Diagram and State Table for a Modulo-8 Counter482

8．7．3 Implementation Using D-Type Flip-Flops484

8．7．4 Implementation Using JK-Type Flip-Flops485

8．7．5 Example-A Different Counter489

8．8 FSM as an Arbiter Circuit492

8．8．1 Implementation of the Arbiter Circuit496

8．8．2 Minimizing the Output Delays for an Fsm499

8．8．3 Summary499

8．9 Analysis of Synchronous Sequential Circuits500

8．10 Algorithmic State Machine(ASM)Charts504

8．11 Formal Model for Sequential Circuits507

Problems509

8．12 Concluding Remarks509

References513

Chapter 9 ASYNCHRONOUS SEQUENTIAL CIRCUITS515

9．1 Asynchronous Behavior516

9．2 Analysis of Asynchronous Circuits519

9．3 Synthesis of Asynchronous Circuits528

9．4 State Reduction540

9．5 State Assignment555

9．5．1 Transition Diagram558

9．5．2 Exploiting Unspecified Next-State Entries561

9．5．3 State Assignment Using Additional State Variables565

9．5．4 One-Hot State Assignment569

9．6 Hazards571

9．6．1 Static Hazards572

9．6．2 Dynamic Hazards576

9．6．3 Significance of Hazards578

9．7 A Complete Design Example579

9．7．1 The Vending-Machine Controller579

9．8 Concluding Remarks583

Problems585

References590

Chapter 10 DIGITAL SYSTEM DESIGN591

10．1 Building Block Circuits592

10．1．1 Flip-Flops and Registers with Enable Inputs592

10．1．2 Shift Registers with Enable Inputs593

10．1．3 Static Random Access Memory (SRAM)595

10．2 Design Examples600

10．2．1 A Bit-Counting Circuit600

10．1．4 SRAM Blocks in PLDs600

10．2．2 ASM Chart Implied Timing Information601

10．2．3 Shift-and-Add Multiplier603

10．2．4 Divider612

10．2．5 Arithmetic Mean623

10．2．6 Sort Operation629

10．3 Clock Synchronization639

10．3．1 Clock Skew640

10．3．2 Filp-Flop Timing Parameters641

10．3．3 Asynchronous Inputs to Flip-Flops644

10．4 Concluding Remarks645

10．3．4 Switch Debouncing645

Problems647

References651

Chapter 11 TESTING OF LOGIC CIRCUITS653

11．1 Fault Model654

11．1．1 Stuck-at Model654

11．1．2 Single and Multiple Faults655

11．1．3 CMOS Circuits655

11．2 Complexity of a Test Set655

11．3 Path Sensitizing657

11．3．1 Detection of a Specific Fault659

11．4 Circuits with Tree Structure661

11．5 Random Tests662

11．6 Testing of Sequential Circuits665

11．6．1 Design for Testability665

11．7 Built-in Self-Test669

11．7．1 Built-in Logic Block Observer673

11．7．2 Signature Analysis675

11．7．3 Boundary Scan676

11．8 Printed Circuit Boards676

11．8．1 Testing of PCBs678

11．8．2 Instrumentation679

11．9 Concluding Remarks680

Problems680

References683

Appendix A VHDL REFERENCE685

A．1 Documentation in VHDL Code686

A．2 Data Objects687

A．2．1 Data Object Names687

A．2．2 Data Object Values and Numbers687

A．2．3 SIGNAL Data Objects687

A．2．4 BIT and BIT_VECTOR Types688

A．2．5 STD_LOGIC and STD_LOGIC_VECTOR Types688

A．2．6 STD_ULOGIC Type689

A．2．7 SIGNED and UNSIGNED Types690

A．2．8 INTEGER Type690

A．2．9 BOOLEAN Type691

A．2．10 ENUMERATION Type691

A．2．12 VARIABLE Data Ojbects692

A．2．13 Type Conversion692

A．2．11 CONSTANT Data Objects692

A．2．14 Arrays693

A．3 Operators693

A．4 VHDL Design Entity694

A．4．1 ENTITY Declaration695

A．4．2 ARCHITECTURE695

A．5 Package697

A．6 Using Subcircuits698

A．6．1 Declaring a COMPONENT in a Package700

A．7 Concurrent Assignment Statements701

A．7．1 Simple Signal Assignment701

A．7．2 Assigning Signal Values Using OTHERS703

A．7．4 Conditional Signal Assignment704

A．7．3 Selected Signal Assignment704

A．7．5 GENERATE Statement705

A．8 Defining an Entity with GENERICs707

A．9 Sequential Assignment Statements707

A．9．1 PROCESS Statement708

A．9．2 IF Statement708

A．9．3 CASE Statement709

A．9．4 LOOP Statements710

A．9．5 Using a Process for a Combinational Circuit710

A．9．6 Statement Ordering711

A．9．7 Using a VARIABLE in a PRocess712

A．10 Sequential Circuits716

A．10．2 D Flip-Flop717

A．10．1 A Gated D Latch717

A．10．3 Using a WAIT UNTIL Statement719

A．10．4 A Flip-Flop with Asynchronous Reset719

A．10．5 Synchronous Reset719

A．10．6 Instantiating a Flip-Flop from a Library721

A．10．7 Registers721

A．10．8 Shift Registers723

A．10．9 Counters725

A．10．10 Using Subcircuits with GENERIC Parameters725

A．10．11 A Moore-Type Finite State Machine728

A．10．12 A Mealy-Type Finite State Machine731

A．10．13 Manual State Assignment for a Finite State Machine731

A．11 Common Errors in VHDL Code734

References738

A．12 Concluding Remarks738

Appendix B TUTORIAL 1739

B．1 Introduction740

B．1．1 Getting Started740

B．2 Design Entry Using Schematic Capture743

B．2．1 Specifying the Project Name744

B．2．2 Using the Graphic Editor744

B．2．3 Synthesizing a Circuit from the Schematic750

B．2．4 Performing Functional Simulation751

B．2．5 Using the Message Processor to Locate and Fix Errors755

B．3 Design Entry Using VHDL757

B．3．1 Specifying the Project Name757

B．3．2 Using the Text Editor757

B．3．4 Performing Functional Simulation759

B．3．3 Synthesizing a Circuit from the VHDL Code759

B．3．5 Using the Message Processor to Debug VHDL Code760

B．4 Design Entry Using Truth Tables760

B．4．1 Using the Waveform Dditor760

B．4．2 Create the Timing Diagram761

B．4．3 Synthesizing a Circuit from the Waveforms763

B．5 Mixing Design-Entry Methods764

B．5．1 Creating a Schematic that Includes a Truth Table764

B．5．2 Synthesizing and Simulating a Circuit from the Schematic765

B．5．3 Using the Hierarchy Display766

B．5．4 Concluding Remarks767

Appendix C TUTORIAL 2769

C．1 Implementing a Circuit in a MAX 7000 CPLD770

C．1．1 Using the Compiler771

C．1．2 Selecting a Chip772

C．1．3 Viewing the Logic Synthesis Options773

C．1．4 Examining the Implemented Circuit774

C．1．5 Running the Timing Simulator775

C．1．6 Using the Floorplan Editor776

C．2 Implementing a Circuit in a FLEX 10K FPGA779

C．3 Downloading a Circuit into a Device781

C．4 Making Pin Assignments783

C．4．1 Assigning Signals to Pins in the Floorplan Editor785

C．4．2 Making Pin Assignments Permanent786

C．5 Concluding Remarks787

Appendix D TUTORIAL 3789

D．1．2 The Ripple-Carry Adder Dode790

D．1 Design Using Hierarchical VHDL Code790

D．1．1 The Full-Adder Subcircuit790

D．1．3 Alternative Style of Code for the Ripple-Carry Adder795

D．1．4 Using the Timing Analyzer Module795

D．2 Using an LPM Module796

D．3 Design of a Sequential Circuit800

D．3．1 Using the Graphic Editor800

D．3．2 Synthesizing a Circuit and Using the Timing Simulator806

D．3．3 Using the Timing Analyzer807

D．3．4 Using VHDL Code807

D．4 Design of a Finite State Machine809

D．4．1 Implementation in a CPLD810

D．4．2 Implementation in an FPGA813

D．5 Concluding Remarks815

Appendix E COMMERCIAL DEVICES817

E．1 Simple PLDs818

E．1．1 The 22V10PAL Device818

E．2 Complex PLDs820

E．2．1 Altera MAX 7000821

E．3 Field-Programmable Gate Arrays822

E．3．1 Altera FLEX 10K823

E．3．2 Xilinx XC4000826

E．4 Transistor-Transistor Logic827

E．4．1 TTL Circuit Families829

References830

INDEX831