射频微电子 原书第2版 英文版PDF|Epub|txt|kindle电子书版本网盘下载

射频微电子 原书第2版 英文版PDF格式电子书版下载

注意：本站所有压缩包均有解压码： 点击下载压缩包解压工具

CHAPTER 1 INTRODUCTION TO RF AND WIRELESS TECHNOLOGY1

1.1 A Wireless World1

1.2 RF Design Is Challenging3

1.3 The Big Picture4

References5

CHAPTER 2 BASIC CONCEPTS IN RF DESIGN7

2.1 General Considerations7

2.1.1 Units in RF Design7

2.1.2 Time Variance9

2.1.3 Nonlinearity12

2.2 Effects of Nonlinearity14

2.2.1 Harmonic Distortion14

2.2.2 Gain Compression16

2.2.3 Cross Modulation20

2.2.4 Intermodulation21

2.2.5 Cascaded Nonlinear Stages29

2.2.6 AM/PM Conversion33

2.3 Noise35

2.3.1 Noise as a Random Process36

2.3.2 Noise Spectrum37

2.3.3 Effect of Transfer Function on Noise39

2.3.4 Device Noise40

2.3.5 Representation of Noise in Circuits46

2.4 Sensitivity and Dynamic Range58

2.4.1 Sensitivity59

2.4.2 Dynamic Range60

2.5 Passive Impedance Transformation62

2.5.1 Quality Factor63

2.5.2 Series-to-Parallel Conversion63

2.5.3 Basic Matching Networks65

2.5.4 Loss in Matching Networks69

2.6 Scattering Parameters71

2.7 Analysis of Nonlinear Dynamic Systems75

2.7.1 Basic Considerations75

2.8 Volterra Series77

2.8.1 Method of Nonlinear Currents81

References86

Problems86

CHAPTER 3 COMMUNICATION CONCEPTS91

3.1 General Considerations91

3.2 Analog Modulation93

3.2.1 Amplitude Modulation93

3.2.2 Phase and Frequency Modulation95

3.3 Digital Modulation99

3.3.1 Intersymbol Interference101

3.3.2 Signal Constellations105

3.3.3 Quadrature Modulation107

3.3.4 GMSK and GFSK Modulation112

3.3.5 Quadrature Amplitude Modulation114

3.3.6 Orthogonal Frequency Division Multiplexing115

3.4 Spectral Regrowth118

3.5 Mobile RF Communications119

3.6 Multiple Access Techniques123

3.6.1 Time and Frequency Division Duplexing123

3.6.2 Frequency-Division Multiple Access125

3.6.3 Time-Division Multiple Access125

3.6.4 Code-Division Multiple Access126

3.7 Wireless Standards130

3.7.1 GSM132

3.7.2 IS-95 CDMA137

3.7.3 Wideband CDMA139

3.7.4 Bluetooth143

3.7.5 IEEE802.11a/b/g147

3.8 Appendix Ⅰ:Differential Phase Shift Keying151

References152

Problems152

CHAPTER 4 TRANSCEIVER ARCHITECTURES155

4.1 General Considerations155

4.2 Receiver Architectures160

4.2.1 Basic Heterodyne Receivers160

4.2.2 Modern Heterodyne Receivers171

4.2.3 Direct-Conversion Receivers179

4.2.4 Image-Reject Receivers200

4.2.5 Low-IF Receivers214

4.3 Transmitter Architectures226

4.3.1 General Considerations226

4.3.2 Direct-Conversion Transmitters227

4.3.3 Modern Direct-Conversion Transmitters238

4.3.4 Heterodyne Transmitters244

4.3.5 Other TX Architectures248

4.4 OOK Transceivers248

References249

Problems250

CHAPTER 5 LOW-NOISE AMPLIFIERS255

5.1 General Considerations255

5.2 Problem of Input Matching263

5.3 LNA Topologies266

5.3.1 Common-Source Stage with Inductive Load266

5.3.2 Common-Source Stage with Resistive Feedback269

5.3.3 Common-Gate Stage272

5.3.4 Cascode CS Stage with Inductive Degeneration284

5.3.5 Variants of Common-Gate LNA296

5.3.6 Noise-Cancelling LNAs300

5.3.7 Reactance-Cancelling LNAs303

5.4 Gain Switching305

5.5 Band Switching312

5.6 High-IP2 LNAs313

5.6.1 Differential LNAs314

5.6.2 Other Methods of IP2 Improvement323

5.7 Nonlinearity Calculations325

5.7.1 Degenerated CS Stage325

5.7.2 Undegenerated CS Stage329

5.7.3 Differential and Quasi-Differential Pairs331

5.7.4 Degenerated Differential Pair332

References333

Problems333

CHAPTER 6 MIXERS337

6.1 General Considerations337

6.1.1 Performance Parameters338

6.1.2 Mixer Noise Figures343

6.1.3 Single-Balanced and Double-Balanced Mixers348

6.2 Passive Downconversion Mixers350

6.2.1 Gain350

6.2.2 LO Self-Mixing357

6.2.3 Noise357

6.2.4 Input Impedance364

6.2.5 Current-Driven Passive Mixers366

6.3 Active Downconversion Mixers368

6.3.1 Conversion Gain370

6.3.2 Noise in Active Mixers377

6.3.3 Linearity387

6.4 Improved Mixer Topologies393

6.4.1 Active Mixers with Current-Source Helpers393

6.4.2 Active Mixers with Enhanced Transconductance394

6.4.3 Active Mixers with High IP2397

6.4.4 Active Mixers with Low Flicker Noise405

6.5 Upconversion Mixers408

6.5.1 Performance Requirements408

6.5.2 Upconversion Mixer Topologies409

References424

Problems425

CHAPTER 7 PASSIVE DEVICES429

7.1 General Considerations429

7.2 Inductors431

7.2.1 Basic Structure431

7.2.2 Inductor Geometries435

7.2.3 Inductance Equations436

7.2.4 Parasitic Capacitances439

7.2.5 Loss Mechanisms444

7.2.6 Inductor Modeling455

7.2.7 Alternative Inductor Structures460

7.3 Transformers470

7.3.1 Transformer Structures470

7.3.2 Effect of Coupling Capacitance475

7.3.3 Transformer Modeling475

7.4 Transmission Lines476

7.4.1 T-Line Structures478

7.5 Varactors483

7.6 Constant Capacitors490

7.6.1 MOS Capacitors491

7.6.2 Metal-Plate Capacitors493

References495

Problems496

CHAPTER 8 OSCILLATORS497

8.1 Performance Parameters497

8.2 Basic Principles501

8.2.1 Feedback View of Oscillators502

8.2.2 One-Port View of Oscillators508

8.3 Cross-Coupled Oscillator511

8.4 Three-Point Oscillators517

8.5 Voltage-Controlled Oscillators518

8.5.1 Tuning Range Limitations521

8.5.2 Effect of Varactor Q522

8.6 LC VCOs with Wide Tuning Range524

8.6.1 VCOs with Continuous Tuning524

8.6.2 Amplitude Variation with Frequency Tuning532

8.6.3 Discrete Tuning532

8.7 Phase Noise536

8.7.1 Basic Concepts536

8.7.2 Effect of Phase Noise539

8.7.3 Analysis of Phase Noise:Approach Ⅰ544

8.7.4 Analysis of Phase Noise:Approach Ⅱ557

8.7.5 Noise of Bias Current Source565

8.7.6 Figures of Merit of VCOs570

8.8 Design Procedure571

8.8.1 Low-Noise VCOs573

8.9 LO Interface575

8.10 Mathematical Model of VCOs577

8.11 Quadrature Oscillators581

8.11.1 Basic Concepts581

8.11.2 Properties of Coupled Oscillators584

8.11.3 Improved Quadrature Oscillators589

8.12 Appendix Ⅰ:Simulation of Quadrature Oscillators592

References593

Problems594

CHAPTER 9 PHASE-LOCKED LOOPS597

9.1 Basic Concepts597

9.1.1 Phase Detector597

9.2 Type-Ⅰ PLLs600

9.2.1 Alignment of a VCO's Phase600

9.2.2 Simple PLL601

9.2.3 Analysis of Simple PLL603

9.2.4 Loop Dynamics606

9.2.5 Frequency Multiplication609

9.2.6 Drawbacks of Simple PLL611

9.3 Type-Ⅱ PLLs611

9.3.1 Phase/Frequency Detectors612

9.3.2 Charge Pumps614

9.3.3 Charge-Pump PLLs615

9.3.4 Transient Response620

9.3.5 Limitations of Continuous-Time Approximation622

9.3.6 Frequency-Multiplying CPPLL623

9.3.7 Higher-Order Loops625

9.4 PFD/CP Nonidealities627

9.4.1 UP and Down Skew and Width Mismatch627

9.4.2 Voltage Compliance630

9.4.3 Charge Injection and Clock Feedthrough630

9.4.4 Random Mismatch between Up and Down Currents632

9.4.5 Channel-Length Modulation633

9.4.6 Circuit Techniques634

9.5 Phase Noise in PLLs638

9.5.1 VCO Phase Noise638

9.5.2 Reference Phase Noise643

9.6 Loop Bandwidth645

9.7 Design Procedure646

9.8 Appendix Ⅰ:Phase Margin of Type-Ⅱ PLLs647

References651

Problems652

CHAPTER 10 INTEGER-N FREQUENCY SYNTHESIZERS655

10.1 General Considerations655

10.2 Basic Integer-N Synthesizer659

10.3 Settling Behavior661

10.4 Spur Reduction Techniques664

10.5 PLL-Based Modulation667

10.5.1 In-Loop Modulation667

10.5.2 Modulation by Offset PLLs670

10.6 Divider Design673

10.6.1 Pulse Swallow Divider674

10.6.2 Dual-Modulus Dividers677

10.6.3 Choice of Prescaler Modulus682

10.6.4 Divider Logic Styles683

10.6.5 Miller Divider699

10.6.6 Injection-Locked Dividers707

10.6.7 Divider Delay and Phase Noise709

References712

Problems713

CHAPTER 11 FRACTIONAL-N SYNTHESIZERS715

11.1 Basic Concepts715

11.2 Randomization and Noise Shaping718

11.2.1 Modulus Randomization718

11.2.2 Basic Noise Shaping722

11.2.3 Higher-Order Noise Shaping728

11.2.4 Problem of Out-of-Band Noise732

11.2.5 Effect of Charge Pump Mismatch733

11.3 Quantization Noise Reduction Techniques738

11.3.1 DAC Feedforward738

11.3.2 Fractional Divider742

11.3.3 Reference Doubling743

11.3.4 Multiphase Frequency Division745

11.4 Appendix Ⅰ:Spectrum of Quantization Noise748

References749

Problems749

CHAPTER 12 POWER AMPLIFIERS751

12.1 General Considerations751

12.1.1 Effect of High Currents754

12.1.2 Efficiency755

12.1.3 Linearity756

12.1.4 Single-Ended and Differential PAs758

12.2 Classification of Power Amplifiers760

12.2.1 Class A Power Amplifiers760

12.2.2 Class B Power Amplifiers764

12.2.3 Class C Power Amplifiers768

12.3 High-Efficiency Power Amplifiers770

12.3.1 Class A Stage with Harmonic Enhancement771

12.3.2 Class E Stage772

12.3.3 Class F Power Amplifiers775

12.4 Cascode Output Stages776

12.5 Large-Signal Impedance Matching780

12.6 Basic Linearization Techniques782

12.6.1 Feedforward783

12.6.2 Cartesian Feedback786

12.6.3 Predistortion787

12.6.4 Envelope Feedback788

12.7 Polar Modulation790

12.7.1 Basic Idea790

12.7.2 Polar Modulation Issues793

12.7.3 Improved Polar Modulation796

12.8 Outphasing802

12.8.1 Basic Idea802

12.8.2 Outphasing Issues805

12.9 Doherty Power Amplifier811

12.10 Design Examples814

12.10.1 Cascode PA Examples815

12.10.2 Positive-Feedback PAs819

12.10.3 PAs with Power Combining821

12.10.4 Polar Modulation PAs824

12.10.5 Outphasing PA Example826

References830

Problems831

CHAPTER 13 TRANSCEIVER DESIGN EXAMPLE833

13.1 System-Level Considerations833

13.1.1 Receiver834

13.1.2 Transmitter838

13.1.3 Frequency Synthesizer840

13.1.4 Frequency Planning844

13.2 Receiver Design848

13.2.1 LNA Design849

13.2.2 Mixer Design851

13.2.3 AGC856

13.3 TX Design861

13.3.1 PA Design861

13.3.2 Upconverter867

13.4 Synthesizer Design869

13.4.1 VCO Design869

13.4.2 Divider Design878

13.4.3 Loop Design882

References886

Problems886

INDEX889